1. Technical Field
One or more embodiments of the invention generally relate to programming of chip multiprocessors. In particular, certain embodiments relate to partitioning an application utilizing a throughput-driven aggregation and mapping approach.
2. Description of Related Art
Chip multiprocessors (CMPs) integrate multiple processors onto one chip. Compared to traditional multiprocessors, CMPs make possible for parallel applications to achieve high performance with lower system cost. Although many CMPs are based on homogeneous architectures, some CMPs (e.g., network processors) are based on a heterogeneous architecture, which composes both general purpose processors and specialized processing elements (PEs). For example, a network processor may include one general purpose processor and multiple processing elements. The general purpose processor may be used to initialize and manage the whole chip, as well as handle control-plane tasks. The PEs, on the other hand, may be configured to handle high rate data-plane processing of packets crucial to the performance of the whole system. The PEs may also support multiple hardware threads to better exploit thread-level parallelism. The PEs may have hardware constraints due to a limited code space on each PE.
In order to achieve high performance of applications running on complex heterogeneous CMPs, developers may have to manually partition an application into tasks and map the tasks to specific processors. The process of manually partitioning an application into tasks and mapping these tasks to appropriate processors on the chip is often time consuming. Such hand-tuned partitioning and mapping decisions are usually made at design time and are based on the performance expectations of the application, the expected workload, and the exact hardware configuration of the system. Consequently, when an application is ported from one platform to another, the performance rarely scales as expected due to mismatches between the mappings, workloads, and the new hardware.